VLSI Courses

RTL DESIGN USING VERILOG (BRIDGE COURSE FOR NON VLSI ENGINEERS)

Course Description

Designing a VLSI chip using FPGA's are very popular these days.

This program is a foundation course for working professionals looking for a job change to the core industry and for engineers in the core industry looking for a lateral change. This program introduces you to the concepts of system design, RTL design using Verilog, programmable ASICs and the role of programmable ASICs in design and development of high density complex IP designs. The course also focuses on the real and practical scenarios using modern FPGA architectures. The course will conclude with an industry oriented project work under the supervision of our expert leads

Pre-requisites

• Understanding of Logic Design concepts
• Familiarity with Verilog Syntax

 Who will Benefit

• BE (Elens and related branches), Engineers working in software domain looking for core jobs
• VLSI Engineers seeking lateral shift to a front end job.

Course Content

1. Overview of Digital Logic Design
2. Introduction to  Verilog HDL
3. Advanced Verilog Design Techniques
4. Basics of Programmable Logic
5. How to begin Simple FPGA Design
6. Design Implementation using Altera Quartus II
7. Efficient Design Practices using Altera Quartus II
8. Project work and board bring up

Course Fee and Duration:

12 days, Rs. 25,000 +Taxes

RTL VERIFICATION USING SYSTEM VERILOG

Course Overview

1. Familiarity with Logic Design concepts
2. Familairity with Verilog Syntax
3. Prior knowledge of RTL Verification concepts using Verilog is desirable

1. VLSI Engineers seeking lateral shift from FPGA to ASIC front-end jobs
2. Engineers looking for RTL verification jobs.
3. Engineers familiar with RTL verification using Verilog looking to acquire skills in System Verilog.

Course Content

1. Introduction to SV
2. Commonly Used Terminologies in SV
3. Data Types
4. Object-Oriented Programming (OOP) Concepts
5. SV Stratified Event Queue/Scheduler
6. SV Tasks and Functions
7. Verification Specific SV Constructs
8. Functional Coverage
9. Verification Plan and SV Testbench Architecture
10. Modelling Testbench Blocks

Course Fee and Duration:

12 days, Rs.48,000+ Taxes

IC LAYOUT DESIGN AND OPTIMIZATION TECHNIQUES (FULL CUSTOM LAYOUT DESIGN).

1. Basic undestanding of MOS Transistor operation

1. VLSI Engineers seeking lateral shift as Full Custom/Mask Layout Engineer
2. Engineers looking to work in areas like Physical IP & Full Custom Analog Layout   design

1. Overview of Full custom IC design
2. Review of Simple circuits
3. Overview of  IC Fabrication Process
4. Introduction to Polygon Editors
5. Layout design concepts
6. Introduction to ESD, LUP, Device Matching techniques and PDK’s
7. Physical Verification and Parasitic Extraction
8. Project Work

STATIC TIMING ANALYSIS OF VLSI DESIGNS

1. Logic Design
2. MOS Transistor Theory

1. VLSI Engineers seeking lateral shift to a back end job.
2. Engineers looking to work for Block level Physical Design Implementation, Place and Route  job profiles.

1. Concepts of STA
2. Clocks & Virtual Clocks
3. Operating Conditions, 
4. Analysis of various Modes & Corners
5. Analyzing  the Timing Reports
6. Signal  Integrity

ASIC PHYSICAL DESIGN (PD) FOR DEEP SUBMICRON PROCESS NODES

Course Overview :

The last phase in the ASIC Design flow involves designing the layout of a Gate Level Netlist using Automatic Place and Route  (AP&R) Tools

 This program introduces you to the concepts used to design Chip-level and Block Level ASIC Layoutsfor Deep sub-micron process nodes using industry standard AP&R (Synopsys) tools. The various implementation steps from Netlist to GDS2 will be covered in detail. Every participant will get the opportunity to practice concepts taught in the class during the concept labssessions. The course will conclude with a project done under the supervision of our leads.

Pre Requisites

1. Logic Design

2. Course on Static Timing Analysis

Who will Benefit

1. VLSI Engineers seeking lateral shift to a back end job.

2. Engineers looking to work for  Block level Physical Design Implementation, Place and Route job domains.

Course Content

1. Introduction to the ASIC Flow

2. Design Setup

3. Chip-Level and Blocl-level implementation steps

4. Floorplan and power planning

5. Placement and Clock Tree Synthesis,

6. Routing, Physical Verification and DFM checks

7. Signal Integrity and Backannotation

8. Sign-off checks and Tapeout

Course Fee and Duration

16 days, Rs.62,000+Taxes

Industry standard sign-off tools from multiple EDA vendors.

All courses will be delivered by VLSI professionals with hands on experience taping out multiple chips used in industry.