VLSI Courses

ADVANCED DIPLOMA IN ASIC DESIGN - RTL VERIFICATION
  • Available : Upto 30
  • Duration : 6 months (1000 hrs)
  • Placement Statistics : 90%
RTL Design using Verilog (Bridge Course for non VLSI Engineers)
  • Available : Upto 30
  • Duration : 12 days (12 Saturdays)
  • Placement Statistics : Enquire at institute for details
RTL Verification using System Verilog
  • Available : Upto 30
  • Duration : 12 days (12 Saturdays)
  • Placement Statistics : Enquire at institute for details
IC Layout design and optimization techniques (Full Custom Layout Design)
  • Available : Upto 30
  • Duration : 12 days (12 Saturdays)
  • Placement Statistics : Enquire at institute for details
Static Timing Analysis of VLSI Designs
  • Available : Upto 30
  • Duration : 12 days (12 Saturdays)
  • Placement Statistics : Enquire at institute for details
ASIC Physical Design (PD) for Deep Submicron process nodes
  • Available : Upto 30
  • Duration : 12 days (12 Saturdays)
  • Placement Statistics : Enquire at institute for details
WhatsApp chat