Course Description

ASIC physical design engineers will convert the gate level netlist from Synthesis into a physical representation (Layout) which will be sent to the fab for manufacturing. As Physical Design engineers you will have to “fit” the design within a given area and meet the power and timing constraints set by the chip lead. Initially you will work as a SoC block level Physical Design Engineer and later on in your career move up the ladder to own the complete chip implementation

ADAD-Physical Design course is designed to make you a competent and productive Physical Design Engineer and learn how to use Synopsys ICC2, Primetime and other tools involved in layout design. The course enables you to acquire knowledge, skills, and practical experience across the entire Backend ASIC Flow (Netlist to GDSII) using Synopsys tools.

The course covers key fundamental concepts of ASIC Physical Design methodology which will enhance the employability of the students. The focus will be on STA, timing closure, PowerPlan and Floorplan, placement, Clock Tree Synthesis (CTS), routing and physical verification (DRC, LVS and ERC). Concepts of parasitic extraction and its impact on timing and power will be discussed.

Learn and Create a Rewarding Career in ASIC Physical Design

This course will be offered in a blended mode. You can choose to learn VLSI Physical Design in online mode or in physical contact class mode or in a blended mode. If you are a working professional or a part time working college graduate you can decide which mode works best for you. Please enquire at the center for more details.

The Lab exercises and Industry Standard Projects that our students are put through instills confidence and the analytical abilities required to work on complex industry challenges in various Deep Sub-Micron Technology Process Nodes.

Course Highlights

  • ADAD Physical Design - 6 months full-time (blended mode) flagship program in VLS
  • Participative & Experiential Learning Model
  • 25% time spent on theory
  • 75% time spent in Labs and Real-Life Projects
  • Access to Semiconductor Technology
  • Work and Learn EDA Tools used by the Industry
  • Learn in a Corporate Environment
1. Overview of transistor theory and network analysis
2. Introduction to Linux and scripting
3. Advanced Logic Design techniques
4. Concept to Chip-design flow for small, large, and analog mixed-signal designs
5. DSM IC Fabrication Flow
6. Fundamentals of RTL-D and Verification using Verilog
7. Fundamentals of Static Timing Analysis
1. Introduction to the ASIC Flow
2. Design Setup and design automation
3. Chip-Level and Block-level implementation steps
4. Floorplan and power planning
5. Placement and Clock Tree Synthesis
6. Routing, Physical Verification DRC, LVS, and DFM checks
7. Signal Integrity and Back Annotation
8. Sign-off checks and Tapeout

Placement Opportunities

RV Skills placement record in VLSI has been an impressive 90%.

After completion of this course, you will be eligible to apply for ASIC Physical Design Engineer jobs. Companies visit us regularly to hire qualified students. Intel, Samsung, Qualcomm, NXP, Broadcom, IBM, Cypress, Mentor Graphics, Synopsys, Synapse, KPIT Cummins, Tata Elxsi, Wipro, HCL, Infosys are few among many companies who regularly acquire Talent from us through our campus placement drives.

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