Course Description

ADAD frontend Verification is designed to make you a competent and productive VLSI Verification Engineer. The course enables you to acquire knowledge, skills, and practical experience in RTL Verification using System Verilog and UVM.

This course will be offered in a blended mode. You can choose to learn VLSI Frontend RTL Verification course in online mode or in physical contact class mode or in a blended mode. If you are a working professional or a part-time working college graduate you can decide which mode works best for you. Please enquire at the center for more details.

The Lab exercises and Industry Standard Projects that our students are put through instills confidence and the analytical abilities required to work on complex industry challenges in various Deep Sub-Micron Technology Process Nodes.

Course Highlights

  • ADAD RTL Verification - 4 months full-time flagship Advance Diploma program
  • Participative & Experiential Learning Model, offered in online/offline/blended modes
  • 25% time spent on theory
  • 75% time spent in Labs and Real-Life Projects
  • Access to Semiconductor Technology
  • Work and Learn in EDA Tools used by the Industry
  • Corporate Practice Environment
1. Overview of transistor theory and network analysis
2. Introduction to Linux and scripting
3. Advanced Logic Design techniques
4. Concept to Chip-design flow for small, large, and analog mixed-signal designs
5. DSM IC Fabrication Flow
6. Fundamentals of RTL-D and Verification using Verilog
7. Fundamentals of Static Timing Analysis
1. Introduction to SV and the ASIC Flow
2. Commonly Used Terminologies in SV
3. SV Data Types
4. Object-Oriented Programming (OOP) Concepts
5. SV Stratified Event Queue/Scheduler
6. SV Tasks and Functions
7. Verification Specific SV Constructs
8. Functional Coverage
9. Verification Plan and SV Testbench Architecture
10. Modelling Testbench Blocks
1. Introduction to UVM
2. UVM Testbench Architecture
3. Simulation phases in UVM
4. UVM Reporting
5. UVM Factory
6. UVM Configuration
7. UVM Transaction
8. UVM Stimulus
9. Transaction Level Modeling (TLM)
10. UVM Analysis Components

Final Project

During the project phase students will work on multiple projects involving, Verification planning, Modeling SV test benches, Modeling UVM Testbenches. Development of SV or UVM Testbench Environment and Verification of different protocols such as Ethernet, SATA, etc. Developing test cases and migrating the test environments.

Placement Opportunities

Our placement record in VLSI has been an impressive 90%.

After completion of this course, you will be eligible to apply for Frontend RTL Verification jobs. Companies visit us regularly to hire qualified students. Intel, Broadcom, IBM, Cypress, Mentor Graphics, Synopsys, Synapse, KPIT Cummins, Tata Elxsi, Wipro, HCL, Infosys are few among many companies who regularly acquire Talent from us through our campus placement drives.

WhatsApp chat